You have been designated to design a $64$ KB n $$ way set associative cache. Each block in the memory is $16$ Bytes. The cache should be Virtually Indexed Physically Tagged type to avoid aliasing. The virtual address is $34$ bits long. The physical address is $32$ bits long. Page offset has the same length $($number of bits$)$ in both the virtual and physical address. The selected page size is $4$ KB$.$ We know that the physical page offset is the total number of bits of the byte offset and cache$/$set index.

a$)$ How many sets can this cache have?

b$)$ How many block frames are there per set in the cache?

c$)$ The characteristics of a $64$ KB n $$ way set associative $($SA$)$ cache, a $4$ KB DM cache, and that of a $64$KB n $$ way SA Way $$ Prediction $($Way $$ P$)$ cache are given in the table below, where n is found in part b$)$ of this problem. Use the Average Memory Access Time to decide if the $64$KB n $$ way SA Way $$ P cache perform better than the $64$KB n $$ way SA$.$

$64$KB n $$ way SA

$4$KB DM

$64$KB n $$ way SA Way$-$P

Hit Rate

$95\%$

$75\%$

$95\%$

Hit Latency

$4$

$2$

$2$ or $4$

Miss Penalty

$25$

$25$

$25$

AMAT

AMAT Calculation