You investigate the possible benefits of a way-predicting L1 cache in this problem. Assume the following .Cache is the cycle time limiter. The system can run at a higher clock rate if the access time of cache is shorter. The access time to the main memory is 10 ns. 25% of instructions are loads and stores. .The number of memory stage in the processor pipeline is l The CPI without stalls caused by data memory accesses is 1.4. Cache 1: Assume that your current data cache is a 64 KB four-way set associative single banked cache. The system clock cycle time is 0.8 ns. Assume the hit time is 1 cycle. , miss penalty is 11 cycles. Miss rate is 0.0033. Cache 2: As an alternative cache organization, you consider a way-predicting cache of the same size and set associativity. If the way prediction is correct, the cache returns result in one cycle. A mispredicted way access that hits in the cache takes one more cycle. The prediction accuracy is 80%. The system clock rate with way-predicting cache is 0.6 ns, similar to a direct mapped cache. The miss penalty is 18 cycles (because the clock is faster). The miss rate is the same as the rate with the 4-way cache (0.0033) e) What is the overall CPI with cache 1? f) What is the overall CPI with cache 2? ) What is the speed up of the system if cache 1 is replaced with cache 2? You investigate the possible benefits of a way-predicting L1 cache in this problem. Assume the following .Cache is the cycle time limiter. The system can run at a higher clock rate if the access time of cache is shorter. The access time to the main memory is 10 ns. 25% of instructions are loads and stores. .The number of memory stage in the processor pipeline is l The CPI without stalls caused by data memory accesses is 1.4. Cache 1: Assume that your current data cache is a 64 KB four-way set associative single banked cache. The system clock cycle time is 0.8 ns. Assume the hit time is 1 cycle. , miss penalty is 11 cycles. Miss rate is 0.0033. Cache 2: As an alternative cache organization, you consider a way-predicting cache of the same size and set associativity. If the way prediction is correct, the cache returns result in one cycle. A mispredicted way access that hits in the cache takes one more cycle. The prediction accuracy is 80%. The system clock rate with way-predicting cache is 0.6 ns, similar to a direct mapped cache. The miss penalty is 18 cycles (because the clock is faster). The miss rate is the same as the rate with the 4-way cache (0.0033) e) What is the overall CPI with cache 1? f) What is the overall CPI with cache 2? ) What is the speed up of the system if cache 1 is replaced with cache 2