you need Personal Computer (Windows OS), ModelSim Student Edition, and Text Editor (Crimson or Notepad++) to design a logic module that will add or subtract two 8-bit numbers. The numbers are A[7:0] and B[7:0]. You may start your design with the FullAdder.vhd, Adder4.vhd and the adder_tb.vhd the files.

First, extend Adder4 to handle 8-bit numbers and name the new file Adder8.vhd. You will need to modify the testbench to confirm that it accurately adds the numbers.

Install the ModelSim on your PC (http://www.model.com) and follow the installation instructions with regard to the license file.

All of the initial files required for the lab are on Blackboard.

When you open ModelSim select FileChange Directory so that you have selected the folder with your source files.

Make sure that you can successfully simulate the Adder4 design shown in the lecture before you start creating your own design. You can execute the simulation by typing do sim.do at the ModelSim command prompt.

Modify the design files, the testbench and the .do file as required to achieve the performance specified in the Design Section.

Make sure you modify the adder_tb.vhd file to verify your design. Extend the loops in the testbench to demonstrate that the 8-bit adder works for all combinations of inputs

adder_tb vhd Test Data SUM SUM in a Process with Wait statements Second, create a new file called Top.vhd. Inside, you need to declare the Adder8 component and instantiate it twice The SEL input determines whether your design is computing A+B (SEL=0) or A-B (SEL = 1). You will need to modify the testbench and declare Top as a component. Instantiate Top in the testbench. Modify the do file to compile Top.vhd. Your simulation should show A+B and A-B. adder_tb.vhd Top vhd A Adders.vhd SUM Test Data SUM (in a Proces with wait A AdderS.vhd 2's comp NO statements) 00000001" SEL SEL adder_tb vhd Test Data SUM SUM in a Process with Wait statements Second, create a new file called Top.vhd. Inside, you need to declare the Adder8 component and instantiate it twice The SEL input determines whether your design is computing A+B (SEL=0) or A-B (SEL = 1). You will need to modify the testbench and declare Top as a component. Instantiate Top in the testbench. Modify the do file to compile Top.vhd. Your simulation should show A+B and A-B. adder_tb.vhd Top vhd A Adders.vhd SUM Test Data SUM (in a Proces with wait A AdderS.vhd 2's comp NO statements) 00000001" SEL SEL