Your first task is to build out the instruction fetch unit. The instruction fetch unit is responsible for fetching the next instruction to execute. Figure $7\mathrm{.}8$ in your book gives you a rough outline of the functionality of this module. The JMP input shown here is$,$ in essence, the PCSrc controller output shown in figure $7\mathrm{.}8.$ This line goes high whenever the CPU is executing some kind of branch. The jump address to be loaded into the program counter is provided via the WBBus input. Since this unit will contain the program counter register, it is essential that it be connected to the system$-$wide Reset and Clk signals. This way, when you reset the CPU, the program counter will reset to zero. A discussion of how this works starts on page $393$ of your textbook.

While building this it$$s important to keep some details in mind. A real ARM CPU uses byte aligned memory and $32-$bit data words. This means that the next instruction is at PC$+4.$ We are using word$-$aligned memory with $16-$bit words. So$,$ for us$,$ the next instruction is at the next location in memory. Also, in ARM, R$15,$ which is the PC register, always holds PC$+8,$ or two instructions ahead. Your book mentions that this is for historical reasons. Consequently, our last register, R$7,$ will always point to the next instruction to be executed, PC$+1.$ This is why we have a PCPlus$1$ output. Note that we must provide the instruction memory address to the memory that is outside of the CPU via the IMAddress pin.

If you build this unit correctly, you should be able to step through memory full of zeros and see the instruction memory increase by one on every step. You should see the contents of the instruction memory on the instruction memory data display. Pressing reset should return the instruction memory address to zero. Please show an image of the completed task.

$$

JMP $0$

Clk$0$

Reset $0$

WBBus $0\mathrm{.}000000$