Your goal is to design and test a register file with 16 registers in System Verilog. A register file is the central storage of a microprocessor. Most operations involve using or modifying data stored in the register file. The register file that will be designed has 16 locations (e.g., RO, R1, etc.). CLK A1 WE3 RDI - RD2 A3 Register - WD3 File Write a System Verilog hardware description of a register file. The register file should conform to the operation specified in the lecture, "Single-Cycle ARM Processor - Datapath," and shown in Figure 1. Below is an example on how create registers in System Verilog. You can test this code in EDAPlayground to see how it executes: Your goal is to design and test a register file with 16 registers in System Verilog. A register file is the central storage of a microprocessor. Most operations involve using or modifying data stored in the register file. The register file that will be designed has 16 locations (e.g., RO, R1, etc.). CLK A1 WE3 RDI - RD2 A3 Register - WD3 File Write a System Verilog hardware description of a register file. The register file should conform to the operation specified in the lecture, "Single-Cycle ARM Processor - Datapath," and shown in Figure 1. Below is an example on how create registers in System Verilog. You can test this code in EDAPlayground to see how it executes