Your project is about writing a Verilog module called bcdadd, but there are actually two other chunks of Verilog code you need in order to test it. The three required modules of Verilog code are:

The definition of a module that starts with module refbcdadd(s, a, b); and computes the BCD result of adding the values of a and b to give the 8-bit result s. Notice that there is no carry out of the 8-bit (two digit) BCD add. This module MUST use Verilog's + operator and doesn't need to be synthesizable. For example, to add two 8-bit BCD values you could convert both to ordinary binary, add them, and then convert the result back to BCD. The ordinary binary value, bin of BCD value bcd would be bin=(10*bcd[7:4])+bcd[3:0];. To convert back, bcd[7:4]=(bin/10)%10; bcd[3:0]=bin%10;. Use as straightforward an implementation as possible; it will serve as your oracle to deliver known correct answers.

The definition of a module that starts with module bcdadd(s, a, b); and implements BCD addition of 8-bit values a and b to give the 8-bit result s. Of course, it may instantiate other combinatorial logic modules to implement its functionality, e.g., you might start with defining a one-bit full adder, then a BCD digit adder, and then this module. Again, you have a free choice of algorithm. However, this module MUST be Verilog code that you author using synthesizable, purely combinatorial, logic -- it is NOT permitted to use word-level Verilog operators (as noted above) in itself nor in anything it instantiates.

The definition of a non-synthesizable module that starts with module testbench; and instantiates a bcdadd which it exhaustively tests for correctness. Note that it is not sufficient to just print what happens for all 10,000 possible combinations of inputs; I don't want just a stimulus module. Who would want to manually check 10,000 lines of output? Incidentally, make sure you test only the 10,000 pairs of valid 8-bit BCD values -- not all 65,536 possible binary bit patterns. Your testbench must not only try each possible input combination, but also must check that the answer from your bcdadd matches the answer from refbcdadd in each case. Your testbench should only output the combinations of inputs for which the answer from bcdadd was wrong. Further, it should count how many input combinations were correct and how many failed. The last line of text output should be generated by Verilog code like:

$display("All cases tested; %d correct, %d failed", correct, failed);