Your task is to implement an ALU shown in Figure $5$ capable of performing R$-$Format Operations

as discussed and uses a single Register File to save $32$bit output from an ALU.

The main features of your design should be:

It reads input operands rs$1$ and rs$2$ for an instruction based on the address of source registers

within the instruction.

The result of ALU shall also be $32-$bits.

The funct$3$ and funct$7$ are given to ALU which performs the specified operation.

The result is then stored back to the destination register rd based on the address of

destination registers within the instruction.

Figure $5.$ An ALU Capable of performing R$-$Format Operations Initializing Register File:

Although it is not a standard way but for this time, in your Registers module, use initial block to initialize

the registers according to the following instructions.

Suppose that the five digits of your roll number are represented in a variable named ROLL.

$($Like Hazoor's roll no is PHDEE$17004,$ therefore ROLL $=17004).$ In your Registers module,

initialize the registers $x_0,x_1,x_2,$dots,$x_{31}$ with the values from the following formula:

$x_n=2^n+n*ROLL$

Example of initializing RAM within your HDL source code: The following example show the initialization

of register contents for your design. For more detailed information please visit $[5]$ and for a useful

discussion is also included at $[6].$ There is an initial block inside your register file which initializes the

contents of $R$ with the values from the file register.data. There are $32$ values of the register.data file and

all values are of $32$ bits. We have used binary data and readmemb function for initializing, you can use

hexadecimal data and readmemh function.

module Register$\_$File$($

$//$ input$/$output ports

;

reg $[31$:$0]$ R $[0$:$31]$; initial begin $readmemb$("$register$.$data", R$,0,31)$; end

$//$ other code goes here endmodule

$//$ contents of the file register.data

$00001110110000011001111011000110$

$01000001010000100101001110010100$ Question # $02(30$ Marks$)$

Write a testbench to simulate and verify your design. Specifically, you need to test by giving the

sequence of instructions from table $1$ and verify the functionality.

Table $1.$ Set of Instructions for Testbench Code

Note:

Your Report should contain a$)$ Verilog Module, b$)$ Verilog Testbench, c$)$ RTL Schematics, d$)$ Resource

Utilization, e$)$ Simulation Waveform, f$)$ Produced Outputs