7–86 Sample-Hold Circuit Figure P7–86 is a simplified diagram of a sample-hold circuit.

When the switch is in position A, the circuit is in the sample mode and the capacitor voltage must charge to at least 99%

of the source voltage VA in less than 1 μs. When the switch is moved to position B, the circuit is in the hold mode and the capacitor must retain at least 99% of VA for at least 1 ms. Select a capacitor that meets these constraints.

Transcribed Image Text:

VA 50 ww Sample Hold A B C: vc(f) FIGURE P7-86 100