7–90 Undesired Ringing A digital clock has become corrupted by a ringing (undesired oscillations) as shown in Figure P7–90(a). The unwanted oscillations can cause false triggers and must be reduced. The clock can be modeled as an RLC series circuit as shown in Figure P7–55

(b) with the voltage taken at node A. The parasitic capacitance is estimated at 0:01 μF and the Thévenin resistance at 330 Ω. From the graph determine the inductanceL. Design an interface circuit that significantly reduces the ringing without significantly reducing the rise time (the time it takes the pulse to go from low to high or vice versa). The transition must occur in less than 80 μs and the “overshoot” (deviation from 0 or 5 V)

must be less than ± 1:5 V. From the graph determine L. Then design a suitable interface to meet the output specifications.

Use standard value components. Use Multisim to validate your design.

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Voltage (V) Clock Signal 9.0 8.0 7.0 6.0- 5.0 4.0 3.0 2.0 1.0 0.0 -1.0. -2.0 -3.0 4.0 00 1000 2000 3000 4000 5000 6000 7000 8000 9000 1.0m 1.im 12m 13m 14m 1.3m Time (s) (a)