Faults of a sequential circuit Figure 5.17 shows a Moore sequential synchronous circuit having one input (x), one output (z), and two internal variables (y1, y2) materialized by two synchronous D Flip-Flops.

1. We suppose that a functional fault made during the design of this circuit has led to the transformation of the NAND gate denoted A into a NOR gate. Analyze the new circuit in order to determine all induced failures .
2. Now we consider the hardware ' stuck-at l ' fault of the line noted a in the figure. Analyze the altered circuit to determine all failures.

Transcribed Image Text:

D1 yl Do D2 Clk Reset Figure 5.17. Sequential circuit -z-y2 y2