Sequential circuit testing We consider the synchronous sequential system in Figure 12.27. We suppose that the initial state is state 1.

1. Check that the input sequences proposed in paragraph 12.3.5, STI and ST2, respectively explore all the states and all the arcs of the graph. For each sequence, determine the sequence of the states and the outputs produced for each sequence.

2. Follow the logical evolution of the signals on the logical circuit for the same test sequences. Is each line of the circuit set to '0' and to '1'

(consequently is it a toggle test)?

3. Comment on the problem experienced in detecting all the circuit single stuck-at faults.

4. Discuss the hypothesis conceming the initial state (state 1) of this sequential system. How can we guarantee that the system is really in state '1' at the beginning of the test?