Signature testing A component tester applies a sequence of 1024 input lO-bit vectors to a device under test (OUT) having 10 inputs and one output. The circuit answers to this input sequence with an output sequence of 1024 bits. A sequential compaction treatment is applied to this output sequence in order to produce a 16-bits signature. So, the lO24-bit stream is split into 64 16-bit words noted Ai. These successive words Ai are 'accumulated' in a 16-bit register R by an XOR logical vector operation: R = R E9 Ai.

1. Which c1asses of failures cannot be observed with this technique?

2. From this, can we deduce the electronic component' s fault c1asses which have not been tested by the tester?