Verification ofthe adder Consider the three-bit adder discussed in Example 10.4), and a design fault which consists in replacing in each half-adder the NAND gate with a NOR gate (see Figure 10.5). Study the faHures induced by this fault according to each of the three previous verification approaches:

1. by inverse transformation and comparison (functional extraction from the logical gate structure), 2. by double transformation with an intermediate model, 3. finally, by double descending transformation.