The linear model of a phase detector (phase-lock loop) can be represented by Figure P6.7 [9].The phase-lock systems are designed to maintain zero difference in phase between the input carrier signal and a local voltage-controlled oscillator. Phase-lock loops find application in color television, missile tracking, and space telemetry. The filter for a particular application is chosen as
F(s) = 10(s + 10)/(s + 1)(s + 100).
We want to minimize the steady-state error of the system for a ramp change in the phase information signal.
(a) Determine the limiting value of the gain KaK = Kv in order to maintain a stable system.
(b) A steady-state error equal to 1° is acceptable for a ramp signal of 100 rad/s. For that value of gain Kv, determine the location of the roots of the system.
Figure P6.7
Phase-lock loop system.

Transcribed Image Text:

Amplifier Voltage-controlled oscillator Filter