Consider the circuit with a depletion load device shown in Figure P16.18.

(a) For \(v_{X}=1.8 \mathrm{~V}\) and \(v_{Y}=0.1 \mathrm{~V}\), determine \(K_{D} / K_{L}\) such that \(v_{O}=0.1 \mathrm{~V}\).

(b) Using the results of part (a), determine \(v_{O}\) when \(v_{X}=v_{Y}=1.8 \mathrm{~V}\).

(c) If the width-to-length ratio of the depletion load is \((W / L)_{L}=1\), determine the power dissipation in the logic circuit for the input conditions listed in parts (a) and (b).

Transcribed Image Text:

Mx Figure P16.18 VDD = 1.8 V VTNI.=-0.6 V KL -000 ly 0 My VTND=0.4 V KD