Consider the pipeline depiction in Figure 12.13b, which is redrawn in Figure 17.25a, with the fetch and decode stages ignored, to represent the execution of thread A. Figure 17.25b illustrates the execution of a separate thread B. In both cases, a simple pipelined processor is used.
a. Show an instruction issue diagram, similar to Figure 17.8a, for each of the two threads.
b. Assume that the two threads are to be executed in parallel on a chip multiprocessor, with each of the two processors on the chip using a simple pipeline. Show an instruction issue diagram similar to Figure 17.8k. Also show a pipeline execution diagram in the style of Figure 17.25.
c. Assume a two-issue superscalar architecture. Repeat part (b) for an interleaved multithreading superscalar implementation, assuming no data dependencies. There is no unique answer; you need to make assumptions about latency and priority.
d. Repeat part c for a blocked multithreading superscalar implementation.
e. Repeat for a four-issue SMT architecture.

Figure 17.25 Two Threads of Execution

1 A1 B1 2 A2 A1 2 B2 B1 3 A3 A2 A1 4 | A3 | A2 | A1 5 | A5 | A4 | A3 | A2 4 B4 B3 B2 BI B3 B2 B3 7 B5 B4 8 A15 9 A16 A15 10 8 B6 B5 B4 B7|B6|B5 | B4 B7 B6 B5 B71B6 B7 A16 A15 10 A16 A15 12 116 12