Figure 17.23 shows the state diagrams of two possible cache coherence protocols. Deduce and explain each protocol, and compare each to MESI.

Figure 17.23 Two Cache Coherence Protocols

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RO) RU) Wo Rii R(i Rii) WoInvalid Valid Invalid Zj) Shared Zj) Wo) lan RG LU) Wo) Z0 RU) Ri) Wo) W) Write to line by processor i R(1)-Read line by processor i Z0) Displace line by cache i Wj) Write to line by processorjG i) R)- Read line by processor j (j i) ZDisplace line by cache j (j i We) Wd) Exclusive Note: State diagrams are for a given line in cache i Rii)