Calculate bias currents and the low-frequency small-signal voltage gain for the CMOS op amp of Fig. 6.58. Use the parameters given in Table 2.4, and assume that X_d=0.1 μm and dX_d/dV_DS = 0.04 μm/V for all the transistors at the operating point. Calculate the input common-mode range assuming that the wells of M₁andM₂are connected to their common-source point. Calculate the low-frequency gain from each supply to the output. Check these cal-culations with SPICE simulations. 

Figure 6.58

Table 2.4

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VDp = 1.5 V 150 150 150 M7 M5 Mg Vi M2 150 M1 150 M9 200 μΑ 5 pF M6 100 M4 50 Mз 50 -VDp = -1.5 V %3D Value Value n-Channel p-Channel Transistor Parameter Symbol Transistor Units Substrate doping NA, Np 5 x 105 Atoms/cm 4 x 10% Gate oxide thickness lox 80 80 Metal-silicon work function -0.6 -0.1 cm²/V-s Channel mobility Minimum drawn channel 450 150 Lawa 0.4 0.4 um length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate width X} 0.15 0.18 La 0.09 0.09 um Ca 0.35 0.35 F/µm Threshold adjust implant (bох dist) impurity type effective depth х, 0.16 0.16 effective surface Ni 4 x 106 3 x 10% Atoms/cm concentration Nominal threshold voltage Polysilicon gate doping V, 0.6 10 -0.8 Napoly 100 Atoms/cm concentration R, Poly gate sheet resistance Source, drain-bulk junction capacitances (zero bias) Source, drain-bulk junction capacitance grading coefficient Cp 0.2 0.4 F/um? 0.5 0.4 C pwo Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading coefficient Source, drain junction built-in potential 1.2 2.4 F/um 0.4 0.3 0.7 0.7 Surface-state density Oss 10" 10" Atoms/cm? Channel-length modulation parameter dX4 dVps 0.02 0.04 um/V