Repeat Problem 7.25 with the following changes: 1. Replace Q 1 with a p-channel MOS transistor, M
Question:
1. Replace Q1 with a p-channel MOS transistor, M1. Replace Q2 and Q3 with n-channel MOS transistors, M2 and M3.
2. Add a resistor of value 1/gm1 from the gate to the source of M1.
3. Take VSUPPLY = 2.5 V.
4. Use the formula for Cdb0 given in Problem 7.17.
5. For all transistors: Ldrwn = 2 µm, Ld = 0.2 µm, Xd = 1 µm, and γ = 0. W1 = 200 µm and W2 =
W3 = 100 µm. Use (1.201) and (1.202) with Ï0 = 0.6 V for the junction capacitances. Use the equations in Problem 7.17 for Cdb0. NMOS data: Vtn = 1 V, kn = 60 µA/V2, λn = 1/(100 V), Cox = 0.7 fF/(µm2), Cj0 = 0.4 fF/(µm2), and Cjsw0 = 0.4 fF/µm. PMOS data: Vtp = 1 V, kp = 20 µA/V2, |λp| = 1/(50 V), Cox = 0.7 fF/(µm2), Cj0 = 0.2 fF/(µm2), and Cjsw0 = 0.2 fF/µm.
Data from Prob. 7.25:
An amplifier stage is shown in Fig. 7.41 where bias current IB is adjusted so that VO = 0 V dc. Take VSUPPLY = 10 V.
(a) Calculate the low-frequency, small-signal trans-resistance Ï o/ii and use the zero-value time-constant method to estimate the 3-dB frequency. Data: npn: β = 100, fT = 500 MHz at IC = 1 mA, Cμ0 = 0.7 pF, Cje = 3 pF (at the bias point), Ccs0 = 2 pF, rb = 0, and VA = 120 V. Assume n = 0.5 and Ï0 = 0.55 V for all junctions. pnp: β = 50, fT = 4 MHz at IC = 0.5 mA, Cμ0 = 1.0 pF, Cje = 3 pF (at the bias point), Cbs0 = 2 pF, rb = 0, and |VA| = 50 V. Assume n = 0.5 and Ï0 = 0.55 V for all junctions.
(b) Repeat (a) if a 20-pF capacitor is connected from collector to base of Q1.
Fig. 7.41:
Step by Step Answer:
Analysis and Design of Analog Integrated Circuits
ISBN: 978-0470245996
5th edition
Authors: Paul R. Gray, Paul J. Hurst Stephen H. Lewis, Robert G. Meyer