A computer has 64 MB of byte-addressable main memory. A proposal is made to design a 1 MB cache memory with a refill line (block) size of 64 bytes.

a. Show how the memory address bits would be allocated for a direct-mapped cache organization.

b. Repeat (a) for a four-way set-associative cache organization.

c. Repeat (a) for a fully associative cache organization.

d. Given the direct-mapped organization and ignoring any extra bits that might be needed (valid bit, dirty bit, etc.), what would be the overall size (“depth” by “width”) of the memory used to implement the cache? What type of memory devices would be used to implement the cache (be as specific as possible)?

e. Which line(s) of the direct-mapped cache could main memory location 1E0027A₁₆ map into? (Give the line number[s], which will be in the range of 0 to [n – 1] if there are n lines in the cache.) Give the memory address (in hexadecimal) of another location that could not reside in cache at the same time as this one (if such a location exists).