A computer has a cache with an access time of 1 cycle and an average hit rate of 95 percent. The miss penalty is 100 cycles. 

a. What is the average cycle time for this computer? 

b. A level 2 cache with a hit rate of 80 percent and a penalty of six cycles is added to this system. What effect does this have on the average cycle time? 

c. A computer with Ll and L2 caches executes 10,000 memory accesses. While the test program is running, 500 misses are recorded to the Ll cache and 300 to the L2 cache. What are the miss rates of the Ll and L2 caches?