Computer Architecture

Question#5: A. Assume that we have a 32-bit processor (with 32-bit words) and that this processor is byte- addressed (i.e. addresses specify bytes). Suppose that it has a 1024-byte cache that is two way set-associative, has 4-word cache lines [block size], and uses FIFO replacement. 1. Split the 32-bit address into "tag", "set", and "cache-line offset" pieces. Tag: Set Address: Block Offset: 2. Below is a series of memory read references set to the cache from part (a). Assume that the cache is initially empty, classify each memory references as a hit or a miss. Also, Identify each miss as either compulsory, conflict, or capacity. Set Address Block Index Hit/Mise? Miss Type Address 0X300 0X206 0X109 0X308 OX1B1 OX2AE 0X3B2 0X205 0X301 B. Suppose that you have a processor with the following specifications. CPI Execution = 1.2, CPU clock rate = 500 MH, Separate Level 1 Caches, Unified Level 2. Instruction miss rate: 1%, Data miss rate: 4%, L1: Write Through to L2 with Write Allocate, and perfect write buffer. L2: Write Back with Write Allocate, with miss rate = 25%. No stall on Li Hit, Access time on L2 = 3 cycles, Memory access time = 100 cycles. Probability a cache block is dirty = 15%. Also Compute the overall CPI. C. Assume that the cache accessed using physical address and the TLB has an access time of 1 cycle and a Hit rate of 90% (TLB is a special cache to translate virtual address to physical address and when data not in TLB it will cost a memory access to get address translation), recalculate the overall CPI from part B. using this information. D. Compare a physical cache and a virtual address cache con pro Physical address cache Virtual address cache