We compare the write bandwidth requirements of write-through versus write-back caches using a concrete example. Let us assume that we have a 64 KB cache with a line size of 32 bytes. The cache will allocate a line on a write miss. If configured as a write-back cache, it will write back all of the dirty line if it needs to be replaced. We will also assume that the cache is connected to the lower level in the hierarchy through a 64-bit-wide (8-byte-wide) bus. The number of CPU cycles for a B-bytes write access on this bus is

a. For a write-through cache, how many CPU cycles are spent on write transfers to the memory for all the combined iterations of the j loop?

b. If the cache is configured as a write-back cache, how many CPU cycles are spent on writing back a cache line?

c. Change PORTION to 8 and repeat part (a).

d. What is the minimum number of array updates to the same cache line (before replacing it) that would render the write-back cache superior?

e. Think of a scenario where all the words of the cache line will be written (not necessarily using the above code) and a write-through cache will require fewer total CPU cycles than the write-back cache.

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10+5-1], where the square brackets represent the "ceiling" function. For example, an 8-byte write would take 10+5 -110 cycles, whereas using the same formula a 12-byte write would take 15 cycles. Answer the following questions while referring to the C code snippet below: #define PORTION 1 base = 8*i; for (unsigned int j = base; j < base + PORTION; j++) //assume j is stored in a register { data[j] = j; }