Consider the addition of a multiplier to the CPU shown in Figure 4.21. This addition will add 300 ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there will no longer be a need to emulate the multiply instruction). 

1. What is the clock cycle time with and without this improvement? 

2. What is the speedup achieved by adding this improvement? 

3. What is the slowest the new ALU can be and still result in improved performance?

Figure 4.21

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PC Add Read address Instruction (31-01 Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction Instruction [15-11] memory Control Instruction [15-0] RegDst Branch MemRead MemtoReg ALUOP MemWrite ALUSro RegWrite Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign- extend 32 Instruction [5-0] Shift left 2, MUX ALU Add, result ALU control Zero ALU result ALU o Max Read data Address Data Write data memory MX