Exercise 4.22 This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a fi ve-stage pipeline, full forwarding, and a predict-taken branch predictor:

a. Label1: lw $1,40($6)

beq $2,$3,Label2 ; Taken add $1,$6,$4 Label2: beq $1,$2,Label1 ; Not taken sw $2,20($4)

and $1,$1,$4

b. add $1,$5,$3 Label1: sw $1,0($2)

add $2,$2,$3 beq $2,$4,Label1 ; Not taken add $5,$5,$1 sw $1,0($2)

4.22.1 [10] <4.8> Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.

4.22.2 [10] <4.8> Repeat Exercise 4.22.1, but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch.

4.22.3 [20] <4.8> One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be “bez Rd,Label” and “bnez Rd,Label”, and it would branch if the register has and does not have a 0 value, respectively. Change this code to use these branch instruction instead of beq. You can assume that register $8 is available for you to use as a temporary register, and that a seq (set if equal) R-type instruction can be used.

Section 4.8 describes how the severity of control hazards can be reduced by moving branch execution into the ID stage. This approach involves a dedicated comparator in the ID stage, as shown in Figure 4.62. However, this approach potentially adds to the latency of the ID stage, and requires additional forwarding logic and hazard detection.

4.22.4 [10] <4.8> Using the fi rst branch instruction in the given code as an example, describe the hazard detection logic needed to support branch execution in the ID stage as in Figure 4.62. Which type of hazard is this new logic supposed to detect?

4.22.5 [10] <4.8> For the given code, what is the speed-up achieved by moving branch execution into the ID stage? Explain your answer. In your speed-up calculation, assume that the additional comparison in the ID stage does not affect clock cycle time.
4.22.6 [10] <4.8> Using the fi rst branch instruction in the given code as an example, describe the forwarding support that must be added to support branch execution in the ID stage. Compare the complexity of this new forwarding unit to the complexity of the existing forwarding unit in Figure 4.62.