Exercise 4.38 This exercise explores energy effi ciency and its relationship with performance.

Problems in this exercise assume the following energy consumption for activity in Instruction Memory, Registers, and Data Memory. You can assume that the other components of the datapath spend a negligible amount of energy.

I-Mem 1 Register Read Register Write D-Mem Read D-Mem Write

a. 100pJ 60pJ 70pJ 120pJ 100pJ

b. 200pJ 90pJ 80pJ 300pJ 280pJ 4.38.1 [10] <4.3, 4.6, 4.14> How much energy is spent to execute an add instruction in a single-cycle design and in the fi ve-stage pipelined design?

4.38.2 [10] <4.6, 4.14> What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it?
4.38.3 [10] <4.6, 4.14> If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by a lw instruction after this change?
The remaining three problems in this exercise assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.
I-Mem Control Register Read or Write ALU D-Mem Read or Write

a. 400ps 300ps 200ps 120ps 350ps

b. 500ps 400ps 220ps 180ps 1000ps 4.38.4 [10] <4.6, 4.14> What is the performance impact of your changes from Exercise 4.38.3?
4.38.5 [10] <4.6, 4.14> We can eliminate the MemRead control signal and have the data memory be read in every cycle, i.e., we can permanently have MemRead=1.
Explain why the processor still functions correctly after this change. What is the effect of this change on clock frequency and energy consumption?
4.38.6 [10] <4.6, 4.14> If an idle unit spends 10% of the power it would spend if it were active, what is the energy spent by the instruction memory in each cycle?
What percentage of the overall energy spent by the instruction memory does this idle energy represent?