Exercise 4.39 Problems in this exercise assume that, during an execution of the program, processor cycles are spent in the following way. A cycle is “spent” on an instruction if the processor completes that type of instruction in that cycle; a cycle is “spent”

on a stall if the processor could not complete an instruction in that cycle because of a stall.

add beq lw sw Control Stalls Data Stalls

a. 35% 20% 20% 10% 10% 5%

b. 25% 10% 25% 10% 20% 10%

Problems in this exercise also assume that individual pipeline stages have the following latency and energy consumption. The stage expends this energy in order to do its work within the given latency. Note that no energy is spent in the MEM stage during a cycle in which there is no memory access. Similarly, no energy is spent in the WB stage in a cycle in which there is no register write. In several of the following problems, we make assumptions about how energy consumption changes if a stage performs its work slower or faster than this.
IF ID EX MEM WB

a. 300ps/120pJ 400ps/60pJ 350ps/75pJ 500ps/130pJ 100ps/20pJ

b. 200ps/150pJ 150ps/60pJ 120ps/50pJ 190ps/150pJ 140ps/20pJ 4.39.1 [10] <4.14> What is the performance (in instructions per second)?
4.39.2 [10] <4.14> What is the power dissipated in watts (joules per second)?
4.39.3 [10] <4.6, 4.14> Which pipeline stages can you slow down and by how much, without affecting the clock cycle time?
4.39.4 [20] <4.6, 4.14> It is often possible to sacrifi ce some speed in a circuit in order to reduce its energy consumption. Assume that we can reduce energy consumption by a factor of X (new energy is 1/X times the old energy) if we increase the latency by a factor of X (new latency is X times the old latency). Now we can adjust latencies of pipeline stages to minimize energy consumption without sacrifi cing any performance. Repeat Exercise 4.39.2 for this adjusted processor.
4.39.5 [10] <4.6, 4.14> Repeat Exercise 4.39.4, but this time the goal is to minimize energy spent per instruction while increasing the clock cycle time by no more than 10%.
4.39.6 [10] <4.6, 4.14> Repeat Exercise 4.39.5, but now assume that energy consumption is reduced by a factor of X2 when latency is made X times longer.
What are the power savings compared to what you computed for Exercise 4.39.2?