Assuming that all gates have equal latencies, what is the length (in gates) of the critical path in your circuit from 4.4.1?

Problem from 4.4.1

Implement the logic for the Control signal 1. Your circuit should directly implement the given expression (do not reorganize the expression to “optimize” it), using NOT gates and 2-input AND, OR, and XOR gates.

When implementing a logic expression in digital logic, one must use the available logic gates to implement an operator for which a gate is not available. Problems in this exercise refer to the following logic expressions:

Transcribed Image Text:

2 b. Control Signal 1 (((A AND B) XOR C) OR (A XOR C)) OR (A XOR B). (((A OR B) AND C) OR (CA OR C) OR (A OR B)) Control Signal 2 (A XOR B) OR (A XOR C) (A AND C) OR (B AND C)