The ARM processor has a few different addressing modes that are not supported in MIPS. The following problems explore these new addressing modes.

For the ARM assembly instructions above, write a sequence of MIPS assembly instructions to accomplish the same data transfer.

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a. b. LDR r0. [rl. #4] LDMIA r0!, [rl-r3] ; r0 = ; rl ; r3 memory [r1+4], memory[r0], memory[r0+8], r1 += 4 r2 = r0 + 3*4 memory [r0+4]