an ISA referred to as the yks architecture (Nole. 2. (30 marks) The following text describes an ISA referred to as contrived example). All instructions in the yks ISA are 2 bytes. The fir mode. All supported addressing modes are give the opcode. Every possible opcode is supported Table 2. MACHINE INSTRUCTION (decimal ADDRESSING MODE Immediate to Register Register to Register are 2 bytes. The first 3 bits represent the addressing ne modes are given in Table 1. The next 5 bits represent code is supported. Some supported opcodes are shown in OD Register to Memory memory location is specified by another register.e. (AXI) 2 oo 301) 100 Register to Memory memory location is specified by immediate 2016 bits value, .g. 1081) Memory to Register (memory location is specified by another register) Immediate to Register 5 10 Table 1 Direct memory to memory operations are not supported. However, they may be Implemented in the higher level assembly language. (In this case the assembler will simply convert the instruction to two separate instructions and use any available register as an intermediary storage) MNEMONIC OPCODE (BINARY) meaning LOAD 00000 Table 2 00001 00010 00011 Load data from source to destination Same as 00000 Adds two operands Subtracts 2 operands. Source from destination MOVEIT PLUS MINUS $ZAX The next 4 bits represent the first operand and is always the destination The last Able represent the second operand and is always the source. There are 16 available registers, AX to PX, Register A is addressed with the value, with 1, C with 2,D with 3, and so on. This continues to the last register registers and their addresses. ntinues to the last register P which has the address 15. Table 3 shows some REGISTER 2x lyte ich MACHINE INSTRUCTION (DECIMAL) 0 DOOD 1 2 OOID OD Table 3 XK16 15 1 Based on the yks architecture, answer the following questions: a. How many different unique full instructions can be accommodated in this ISA? (Remember to take out the unsupported instructions) 14 marks) b. How many different unique opcodes can be accommodated? (1 mark [1 mark] c. What is the largest value of an operand? d. What is the most likely size of register DX? 11 mark] Jo e. [9 marks) Convert the following high-level assembly language program to machine code. (As is common in assembly language, memory references are made using a register in square brackets) LOAD JX, 10H LOAD BX, (JX PLUS JX, BX lolo MOVEIT (AX), JX LOAD BX, 08H LOAD (AX). [BX] (11 400) Du memory 2 & machine code instructions into assembly language. f. 15 marks] des, fone Convert the following machine code instruc 1. 00 obooo doo doooo ii. 0110001110100101 lil. 1010001100010000 ofol selge, ear 8. [3 marks] A given single-cycle (non-pipelined) microproces architecture. It uses 1 clock cycle for the fet stage and 1 clock cycle for the execute stage no matter the instrucao if the processor takes 26.25ns to execute the program in question 2.e, w the frequency of its clock? ycle (non-pipelined) microprocessor implements the yks It uses 1 clock cycle for the fetch stage, 1 clock cycle for the decode (For each instruction, remember to take into consideration the time for the Fetch, Decode, and execute stages. For simplicity, assume the write-back stage is embedded in the execute stage.) h. [6 marks] How long would it take the processor in question 2.g. to execute the same program if it is modified to use a simple 3-stage pipeline using the same clock. an ISA referred to as the yks architecture (Nole. 2. (30 marks) The following text describes an ISA referred to as contrived example). All instructions in the yks ISA are 2 bytes. The fir mode. All supported addressing modes are give the opcode. Every possible opcode is supported Table 2. MACHINE INSTRUCTION (decimal ADDRESSING MODE Immediate to Register Register to Register are 2 bytes. The first 3 bits represent the addressing ne modes are given in Table 1. The next 5 bits represent code is supported. Some supported opcodes are shown in OD Register to Memory memory location is specified by another register.e. (AXI) 2 oo 301) 100 Register to Memory memory location is specified by immediate 2016 bits value, .g. 1081) Memory to Register (memory location is specified by another register) Immediate to Register 5 10 Table 1 Direct memory to memory operations are not supported. However, they may be Implemented in the higher level assembly language. (In this case the assembler will simply convert the instruction to two separate instructions and use any available register as an intermediary storage) MNEMONIC OPCODE (BINARY) meaning LOAD 00000 Table 2 00001 00010 00011 Load data from source to destination Same as 00000 Adds two operands Subtracts 2 operands. Source from destination MOVEIT PLUS MINUS $ZAX The next 4 bits represent the first operand and is always the destination The last Able represent the second operand and is always the source. There are 16 available registers, AX to PX, Register A is addressed with the value, with 1, C with 2,D with 3, and so on. This continues to the last register registers and their addresses. ntinues to the last register P which has the address 15. Table 3 shows some REGISTER 2x lyte ich MACHINE INSTRUCTION (DECIMAL) 0 DOOD 1 2 OOID OD Table 3 XK16 15 1 Based on the yks architecture, answer the following questions: a. How many different unique full instructions can be accommodated in this ISA? (Remember to take out the unsupported instructions) 14 marks) b. How many different unique opcodes can be accommodated? (1 mark [1 mark] c. What is the largest value of an operand? d. What is the most likely size of register DX? 11 mark] Jo e. [9 marks) Convert the following high-level assembly language program to machine code. (As is common in assembly language, memory references are made using a register in square brackets) LOAD JX, 10H LOAD BX, (JX PLUS JX, BX lolo MOVEIT (AX), JX LOAD BX, 08H LOAD (AX). [BX] (11 400) Du memory 2 & machine code instructions into assembly language. f. 15 marks] des, fone Convert the following machine code instruc 1. 00 obooo doo doooo ii. 0110001110100101 lil. 1010001100010000 ofol selge, ear 8. [3 marks] A given single-cycle (non-pipelined) microproces architecture. It uses 1 clock cycle for the fet stage and 1 clock cycle for the execute stage no matter the instrucao if the processor takes 26.25ns to execute the program in question 2.e, w the frequency of its clock? ycle (non-pipelined) microprocessor implements the yks It uses 1 clock cycle for the fetch stage, 1 clock cycle for the decode (For each instruction, remember to take into consideration the time for the Fetch, Decode, and execute stages. For simplicity, assume the write-back stage is embedded in the execute stage.) h. [6 marks] How long would it take the processor in question 2.g. to execute the same program if it is modified to use a simple 3-stage pipeline using the same clock