The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4 51, and assume the following clock cycle time, ALU latency, and Mux latency Figure 4 51 How much time does the control unit have to generate the ALUSrc control signal Compare this to a single cycle organization a b Instruction LW R1,32(R2) OR R1, R5, R6 Clock Cycle Time 50ps 200ps ALU Latency 30ps 170ps Mux Latency 15ps 25ps

Question: The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the

The first three problems in this exercise refer to the execution of the following instruction in the pipelined datapath from Figure 4.51, and assume the following clock cycle time, ALU latency, and Mux latency: a. b. Instruction LW R1,32(R2) OR R1, R5, R6 Clock Cycle Time 50ps 200ps ALU Latency 30ps 170ps Mux Latency

Figure 4.51 14 MUX PC Address Add Instruction memory IFAD Instruction Read register 1 Read register 2 Write register

How much time does the control unit have to generate the ALUSrc control signal? Compare this to a single-cycle organization.

a. b. Instruction LW R1,32(R2) OR R1, R5, R6 Clock Cycle Time 50ps 200ps ALU Latency 30ps 170ps Mux Latency 15ps 25ps

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