What is the clock cycle time in a pipelined and non-pipelined processor? In this exercise, we examine

Question:

What is the clock cycle time in a pipelined and non-pipelined processor?

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: a. b. IF 250ps 200ps ID 350ps 170ps EX 150ps 220ps MEM 300ps 210ps WB 200ps 150ps