please solve orgnization computer

1. (7 points) In a 5-pipeline processor, assume that the stages of the datapath have the fol- lowing latencies: IF ID EX MEM WB 350 ps 250 ps 100 ps 400 ps 150 ps Also, assume that instructions executed by the processor are broken down as follows: ALU/Logic Jump/Branch Load Store 55 % 10 % 25 % 10 % Answer the following questions: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an Id instruction in a pipelined and non-pipelined pro- cessor? (e) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit