Show how outputs 5 and 6 of decoder F3 in Fig. 7-7 are to be connected to
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Show how outputs 5 and 6 of decoder F3 in Fig. 7-7 are to be connected to the program counter PC.
Fig. 7-7
Transcribed Image Text:
FI PCTAR 3 x 8 decoder 7 6 5 4 3 210 DRTAR DRTAC ADD Select Load From PC 0 F2 Multiplexers AR 3 x 8 decoder 7 6 5 4 3 2 10 From DR (0-10) AND Load Arithmetic logic shift unit AC F3 3 x 8 decoder 7 6 5 4 3 2 1 0 Clock
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