An article in the AT&T Technical Journal (March/April 1986, Vol. 65, pp. 39-50) describes the application of two-level factorial designs to integrated circuit manufacturing. A basic processing step is to grow an epitaxial layer on polished silicon wafers. The wafers mounted on a susceptor are positioned inside a bell jar, and chemical vapors are introduced. The susceptor is rotated and heat is applied until the epitaxial layer is thick enough. An experiment was run using two factors: arsenic flow rate (A) and deposition time (B). Four replicates were run, and the epitaxial layer thickness was measured (in tun). The data are shown below:

(a) Estimate the factor effects.

(b) Conduct an analysis of variance. Which factors are important?

(c) Write down a regression equation that could be used to predict epitaxial layer thickness over the region of arsenic flow rate and deposition time used in this experiment.

(d) Analyze the residuals. Are there any residuals that should cause concern?

(e) Discuss how you might deal with the potential outlier found in part (d).

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Replicate Factor Levels A B I II III IV Low (-) High (+) 14.037 16.165 13.972 13.907 A 55% 59% 13.880 13.860 14.032 13.914 Long (15 min) 14.821 14.757 14.843 14.878 Short + 14.888 14.921 14.415 14.932 (10 min) + +