Sketch a schematic of the circuit described by the following HDL code. Simplify the schematic so that it shows a minimum number of gates. 

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SystemVerilog VHDL module exercise2(input logic [3:0] a. output logic (1:0] y): library IEEE; use IEEE.STD_LOGIC_1164.all; entity exercise2 is port(a: in STD_LOGIC_VECTOR(3 downto 0); y: out STD LOGIC_VECTOR(1 downto 0)): always_comb if (a[0]) y =2'b11; else if (a[1]) y= 2'b10; else if (a[2]) y = 2'b01; else if (a[3]) y = 2'b00; end: architecture synth of exercise2 is begin process(all) begin y = a[1:0]: else endmodule a(0) then y <= "11"; elsif a(1) then y <= "10"; elsif a(2) then y <= "01"; elsif a(3) then y <= "00"; if else y <= a(1 downto 0): end if: end process: end: