Calculate the maximum allowable clock skew in Figure 15.19. Indicate between which pair of flip-flops the skew occurs and whether it will trigger a setup or hold violation. Use flip-flop specification A and a 2 ns clock. You may want to enumerate all possible paths and write the setup and hold equations. 

Data in Figure 15.19.

Logic A t = 10 ps td = 400 ps Logic B tc = 100 ps td = 200 ps Logic C t = 30 ps td = 50 ps X Y N