Design and code a FIFO synchronizer that uses a presence bit for each register instead of head and tail pointers. When the input writes a value into a register, the corresponding presence bit is marked as full. When the output reads a value, the corresponding presence bit is marked empty. You will need a bank of presence bits in each clock domain. Assume that the RAM can be safely read asynchronously, but is written synchronously in clock domain 1. You should have room for four entries in the shared RAM.