Question: Four RAM memories are connected to CPU busses as shown here. Assume that the following RAM component is available.module SRAM(cs-b, we-b, oe-b, address, data);input cs-b,we-b,oe-b;input[14:0]

Four RAM memories are connected to CPU busses as shown here. Assume that the following RAM component is available.module SRAM(cs-b, we-b, oe-b, address, data);input cs-b,we-b,oe-b;input[14:0] address;inout[7:0] data;endmoduleWrite a Verilog code segment that will connect the four RAMs to the busses. Use a generate statement and a named association.

CPU abus[14:0] dbus[31:0] sel wr 15 32 15 15 15 15 15

CPU abus[14:0] dbus[31:0] sel wr 15 32 15 15 15 15 15 data[31:24] addr[14:0] data[23:16] addr[14:0] data[15:8] addr[14:0] data[7:0] addr[14:0] Ram3 Ram2 Ram1 Ram0 CS WE OE CS WE OE CS WE OE CS WE OE

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