In Question 9.24, it is assumed that data should be written into the register file during the write-back stage of an instruction before a subsequent instruction can read it. This introduces two idle cycles if instruction i + 1 is dependent on instruction i. A technique that many processors use to solve this problem is data forwarding. If an instruction needs the result from an instruction ahead of it, the result is forwarded to the current instruction. This can be done by having multiplexers at the input of the ALU, which take the operand from the register file, the forwarding path from the output of the ALU, or the output of the memory-access stage (fourth stage). The dependencies between instructions are clearly identified, and then the multiplexers are appropriately controlled to forward the correct data. 

(a) Design a pipelined implementation of the MIPS design shown in Figure 9-8 with data forwarding. Draw a block diagram indicating the forwarding hardware. Write Verilog code, synthesize it for an FPGA target, and implement it on an FPGA prototyping board. While implementing on the prototyping board, use an 8-Hz clock as in Exercise 9.16.
(b) Compare the performance of the code in Exercises 9.12 and 9.13 using this design, with the design in Exercise 9.24 and the design in Figure 9-8.