Consider the situation of Figure 5 67 for each of the following sets of timing values For each, indicate whether or not flip flop Q 2 will respond correctly Figure 5 67 (a) Each FF TPLH 12 ns tpHL 8 ns ts 5 ns th 8 ns tpHL 6ns 5ns (b) NAND gate tpLH (c) INVERTER tpLH 7ns tpHL (d) Each FF tpLH 10 ns...

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Consider the situation of Figure 5-67 for each of the following sets of timing values. For each,

Question:

Consider the situation of Figure 5-67 for each of the following sets of timing values. For each, indicate whether or not flip-flop Q₂ will respond correctly.

(a)* Each FF: TPLH = 12 ns; tpHL = 8 ns; ts = 5 ns; th 8 ns; tpHL 6ns 5ns (b) NAND gate: tpLH (c) INVERTER:

Figure 5-67

CLOCK 1 +5 V D O CLK total delay = 1 (a) CLOCK 2 D CLK Q CLOCK 1 CLOCK 2 Q 65 15 5 13 = = assume X HIGH skew 13 skew = combined delay of NAND gate and INVERTER IPLH