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computer science
digital systems principles and application

Questions and Answers of Digital Systems Principles And Application

(a) A five-bit DAC has a current output. For a digital input of 10100, an output current of 10 mA is produced. What will IOUT be for a digital input of 11101?(b) What is the largest value of output
What is the main advantage of a SAC over a digital-ramp ADC?
How would the address counter be changed if there were eight analoginputs?
Describe the steps in a computer data acquisition process.
A certain memory has a capacity of 8K × 16. How many bits are in each word? How many words are being stored? How many memory cells does this memory contain?
What is a “page” of memory?
What is programming or burning-in a ROM?
What is a major advantage of using CDs and DVDs to store digital information?
Where does the word flash come from?
True or false: When memory chips are combined to form a module with a larger word size or capacity, the CS inputs of each chip are always connected together.
What is a data-rate buffer?
Describe the conditions at each input and output when the data word 1110 is to be written into address location 01101. (See Figure 12-4.)Figure 12-4 0100 0110 1001 1 1 1
What are the main elements of a function generator?
True or False: RAM is the only memory device that is randomly accessed.
What device places data on the data bus during a write cycle?
True or false: A volatile memory will lose its stored data when electrical power is interrupted.
What are the functions of the R̅A̅S̅ and C̅A̅S̅ signals?
A certain memory stores 8K 16-bit words. How many data input and data output lines does it have? How many address lines does it have? What is its capacity in bytes?
True or false:(a) In the R̅A̅S̅-only refresh method, the C̅A̅S̅ signal is held LOW.(b) C̅A̅S̅-before-R̅A̅S̅ refresh can be used only by DRAMs with on-chip refresh control circuitry.
What does EDO stand for?
How is an EPROM erased?
True or false: When memory chips are combined for a larger capacity, each chip is connected to the same data bus lines.
How does a circular buffer differ from a linear buffer?
What is the function of a flash memory’s command register?
A certain memory has a capacity of 4K × 8.(a) How many data input and data output lines does it have?(b) How many address lines does it have?(c) What is its capacity in bytes?
Which register will be enabled by input address 1101?
What RAM timing parameters determine its operating speed?
Explain the difference between SAM and RAM.
What is the function of the MUX signal?
Define each of the following terms.(a) RAM(b) RWM(c) ROM(d) Internal memory(e) Auxiliary memory(f) Capacity(g) Volatile(h) Density(i) Read(j) Write
What term is used for accessing several consecutive memory locations?
True or false: There is no way to erase only a portion of an EPROM’s memory.
If two of the address lines are excluded from the address decoding scheme of a memory chip, how many blocks of memory will the same chip occupy?
Why are logic functions NAND/NOR used to describe flash memory?
What input address will enable register 7?
Explain the difference between RWM and ROM.
(a) What are the three buses in a computer memory system?(b) Which bus is used by the CPU to select the memory location?(c) Which bus is used to carry data from memory to the CPU during a read
How does DDR double the data rate?
What function is performed by PROM and EPROM programmers?
Which flash configuration is byte eraseable?
Refer to Figure 12-6. Determine the data outputs for each of the following input conditionsFigure 12-6 (a) [A] = 1011; CS = 1, OE = 0 (b) [A] = 0111; CS = 0, OE = 0
Describe the internal architecture of a ROM that stores 4K bytes and uses a square register array.
True or false: A dynamic memory will hold its data as long as electrical power is applied.
What was the main improvement in moving from DDR to DDR2 to DDR3 to DDR4?
Refer to Figure 12-7.(a) What register is enabled by input address 1011?(b) What input address code selects register 4?Figure 12-7 CS OE- Ao A₁→ A₂ A₂ ROW
MROMs can be used to store tables of mathematical functions. Show how the MROM in Figure 12-9 can be used to store the function y = x2 + 3, where the input address supplies the value for x, and the
What EPROM shortcomings are overcome by EEPROMs?
Which flash configuration is used in USB thumb drives?
What are the major drawbacks of EEPROM?
A certain ROM has a capacity of 16K × 4 and an internal structure like that shown in Figure 12-7.(a) How many registers are in the array?(b) How many bits are there per register?(c) What size
The 2125A is a static-RAM IC that has a capacity of 1K × 1, one active-LOW chip select input, and separate data input and output. Show how to combine several 2125A ICs to form a 1K × 8 module.
What type of ROM can erase one byte at a time?
We want to combine several 2K × 8 PROMs to produce a total capacity of 8K × 8. How many PROM chips are needed? How many address bus lines are required?
(a) True or false: ROMs cannot be erased.(b) What is meant by programming or burning a ROM?(c) Define a ROM’s access time.(d) How many data inputs, data outputs, and address inputs are needed for a
What would be needed to expand the memory of Figure 12-37 to 32K × 8? Describe what address lines are used.Figure 12-37
How is a logic 1 represented in a UVEPROM cell?
Figure 12-40 shows how data from a ROM can be transferred to an external register. The ROM has the following timing parameters: tACC = 250 ns and tOE = 120 ns. Assume that the new address inputs have
Repeat Problem 12-11 if the address inputs are changed 70 ns prior to the TRANSFER pulse.Data from Problem 12-11Figure 12-40 shows how data from a ROM can be transferred to an external register. The
How is logic 1 represented in a EEPROM cell?
Which transistors in Figure 12-9 will be conducting when A1 = A0 = 1 and E̅N̅ = 0?Figure 12-9 A₁ Ap 2 EN -C Address A₁ Ao 0 0 0 1 BOTF 1
For each item below, indicate the type of memory being described: MROM, PROM, EPROM, EEPROM, flash. Some items will correspond to more than one memory type.(a) Can be programmed by the user but
Change the MROM connections in Figure 12-9 so that the MROM stores the function y = 3x + 5.Figure 12-9 A₁ Ap 2 EN -C Address A₁ Ao 0 0 0 1 BOTF 1
Figure 12-41 shows a simple circuit for manually programming a 2732 EPROM. Each EPROM data pin is connected to a switch that can be set at a 1 or a 0 level. The address inputs are driven by a 12-bit
Another ROM application is the generation of timing and control signals. Figure 12-43 shows a 16 × 8 ROM with its address inputs driven by a MOD-16 counter so that the ROM addresses are incremented
Change the program stored in the ROM of Problem 12-18 to generate the D7 waveform of Figure 12-44.Figure 12-44.Data from Problem 12-8Another ROM application is the generation of timing and control
Figure 12-42 shows a small flash memory chip connected to a CPU over a data bus and an address bus. The CPU can write to or read from the flash memory array by sending the desired memory address and
Refer to the function generator of Figure 12-20.(a) What clock frequency will result in a 100-Hz sine wave at the output?(b) What method could be used to vary the peak-to-peak amplitude of the sine
The system shown in Figure 12-45 is a waveform (function) generator. It uses four 256-point look-up tables in a 1-Kbyte ROM to store one cycle each of a sine wave (address 000–0FF), a positive
Refer to Problem 12-21.(a) If counter A is initially loaded with 0, what values must be loaded into counters B and C so that A lags B by 90° and A lags C by 180°?(b) If counter A is initially
A certain static RAM has the following timing parameters (in nanoseconds):(a) How long after the address lines stabilize will valid data appear at the outputs during a read cycle?(b) How long will
(a) Draw the logic symbol for an MCM101514, a CMOS static RAM organized as a 256K × 4 with separate data in and data out, and an active-LOW chip enable.(b) Draw the logic symbol for an MCM6249, a
Figure 12-46(a) shows a circuit that generates the R̅A̅S̅, C̅A̅S̅, and MUX signals needed for proper operation of the circuit of Figure 12-27(b). The 10-MHz master clock signal provides the
Draw the logic symbol for the TMS4256, which is a 256K × 1 DRAM. How many pins are saved by using address multiplexing for this DRAM?
Show how to connect two 74157 multiplexers to provide the multiplexing function required in Figure 12-27(b).Figure 12-27(b) CPU A15
Refer to the signals in Figure 12-29. Describe what occurs at each of the labeled time points.Figure 12-29 MUX RAS CAS Address DATA OUT 1 1 1 1 1 to ROW 1 1 1 1 1 COLUMN 1 I 1 1 DATA I I VALID I 1 15
Repeat Problem 12-28 for Figure 12-30.Figure 12-30Data from Problem 12-28Refer to the signals in Figure 12-29. Describe what occurs at each of the labeled time points.Figure 12-29
The 21256 is a 256K × 1 DRAM that consists of a 512 × 512 array of cells. The cells must be refreshed within 4 ms for data to be retained. Each time a C̅A̅S̅ before R̅A̅S̅ refresh cycle
The SDRAM on the DE1 board from Terasic contains an 8 Mbyte SDRAM. This IC has 12 address (A11–A0). All 12 address bits are latched into the row address register by R̅A̅S̅. The IC has two input
Describe how to modify the circuit of Figure 12-35 so that it has a total capacity of 16K × 8. Use the same type of PROM chips.Figure 12-35 A15 A₁4 A13 A12 दददददद..... A11 A10 Control
Show how to combine two 6264 RAM chips (use the internet to look up the data sheet) to produce an 8K × 16 module.
Show how to connect two of the 6264 RAM chips (use the internet to look up the data sheet) to produce a 16K × 8 RAM module. The circuit should not require any additional logic. Draw a memory map
Modify the decoding circuit of Figure 12-35 to operate from a 16-line address bus (i.e., add A13, A14, and A15). The four PROMs are to maintain the same hex address ranges.Figure 12-35
For the memory system of Figure 12-36, assume that the CPU is storing one byte of data at system address 4000 (hex).(a) Which chip is the byte stored in?(b) Is there any other address in this system
Draw the complete diagram for a 256K × 8 memory that uses RAM chips with the following specifications: 64K × 4 capacity, common input/output line, and two active-LOW chip select inputs.
Name three resources that have been added to most FPGA ICs to make them more capable of implementing any digital systems.
Describe each of the following major digital system categories:(a) Standard logic(b) ASICs(c) Microprocessor/DSP
Verify that the correct fuses are blown for the O2, O1, and O0 functions in Figure 13-5(b).Figure 13.5(b) 03 - AB+CD; 0₂ - ABC 0₁ - ABCD + ABCD; O-A+BD +
What are the three major categories of digital systems?
What is a PLD?
What characteristics are carried over from the SPLDs to MAX/7000 CPLDs?
Describe the improvements with each new generation of FPGA.
Name three factors that are generally considered when making design engineering decisions.
What would output O1 be in Figure 13-3 if fuses 1 and 2 were blown?Figure 13-3 TA B Input lines B AND array AB AB AB AB J 1 Fuses 17 Sum of product outputs AB AB AB AB Product lines OR array
What is the major disadvantage of a microprocessor/DSP design?
Fill in the blanks.A PAL has a hard-wired ____________ array and a programmable ____________ array.
What were the new improvements of the MAX7000S series?
Why is a microprocessor/DSP system called a software solution for a design?
What does ASIC stand for?
Fill in the blanks.A PROM has a hard-wired ____________ array and a programmable ____________ array.
What does an X represent on a PLD diagram?

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