Refer to Problem 12-21.

(a) If counter A is initially loaded with 0, what values must be loaded into counters B and C so that A lags B by 90° and A lags C by 180°?

(b) If counter A is initially loaded with 0, what values must be loaded into counters B and C to generate a three-phase sine wave with 120° shift between each output?

(c) What must the frequency of pulses on DAC_OUT be in order to generate a 60-Hz sine wave output?

(d) What is the maximum frequency of the CLK input?

(e) What is the maximum frequency of the output waveforms?

(f) What is the purpose of the function select counter?

Data from Problem 21

The system shown in Figure 12-45 is a waveform (function) generator. It uses four 256-point look-up tables in a 1-Kbyte ROM to store one cycle each of a sine wave (address 000–0FF), a positive slope ramp (address 100–1FF), a negative slope ramp (200–2FF), and a triangle wave (300–3FF). The phase relationship among the three output channels is controlled by the values initially loaded into the three counters. The critical timing parameters are t_{pd(ck-Q and OE–Q max)}, counters = 10 ns, latches = 5 ns, and t_ACC ROM = 20 ns. Study the diagram until you understand how it operates and then answer the following:

In Figure 12-45, the three latches on the left perform a function that represents one of the basic building blocks of digital systems as presented in Chapter 9. Which function is it?

The four latches that are fed by the ROM serve to implement another basic building block of digital systems. Which function is it?

Why are the octal latches that feed the DACs necessary?

What number must be on the MOD 4 function select counter to produce each of the following waveforms: triangle; sine; negative ramp; positive ramp?

Figure 12-45

Transcribed Image Text:

Phase A Load Phase B Load- Phase с Load Eight-bit binary counters asynchronous load tristate outputs CLK [8] [8] [8] D₂ Q₂ Do Qo OE D7 Q7 Do Qo OE [8] [8] D₂ Q₂ [8] Do Qo OE [8] Function select MOD-4 Ap 2 1K X 8 ROM A7 AB Ag D₂ Do 18 D 14 D QD [8] [8] [8] [8] Octal latches D7 Q7 Do Qo En D7 Q7 Do Qo En D7 Q7 Do Qo ਕੁਦਰ D Q D Q D Q CLR CLR CLR PRE En DAC-Out Voc [8] [8] [8] Octal latches D₂ Q7 Do Qo En D₂ Q₂N [8] Do Qo En D7 Q7 Do Qo [8] En [8] Eight-bit DACs D₁ Do DAC A D₂ Do DAC B D₂ Do DAC C Out A Out B Out C