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computer science
digital systems principles and application

Questions and Answers of Digital Systems Principles And Application

How many rows on the scanned keyboard are activated at any point in time?
If two keys in the same column are pressed simultaneously, which key will be encoded?
What is the purpose of the D flip-flop on the DAV pin?
Will the time between the key being pressed and DAV going HIGH always be the same?
When are the data output pins in the Hi-Z state?
Describe the input signal requirements for transferring [A] → [C].
A technician tests the circuit of Figure 9-4 as described in Example 9-7 and finds that the correct output is activated for each possible input code except those listed in Table 9-8. Examine this
Suppose that a 22-Ω resistor was mistakenly used for the g segment in Figure 9-8. How would this affect the display? What possible problems could occur?Figure 9-8 D C BCD input
The timing diagram in Figure 9-77 is applied to Figure 9-19. Draw the output waveform Z.Figure 9-77Figure 9-19 S ப பரீ th Tட
Figure 7-73 shows an eight-bit shift register that could be used to delay a signal by 1 to 8 clock periods. Show how to wire a 74151 to this shift register in order to select the desired Q output and
(a) Use the idea from Problem 9-29 to arrange several 74151 1-of-8 multiplexers to form a 1-of-64 multiplexer.(b) Use a Quartus II megafunction to create a 1-of-2 MUX, a 1-of-4 MUX, and a 1-of-8
(a) Show how two 74157s and a 74151 can be arranged to form a 1-of-16 multiplexer with no other required logic. Label the inputs I0 to I15 to show how they correspond to the select code.(b) Create a
Figure 9-79 shows how a multiplexer can be used to generate logic waveforms with any desirable pattern. The pattern is programmed using eight SPDT switches, and the waveform is repetitively produced
Change the MOD-8 counter in Figure 9-79 to a MOD-16 counter, and connect the MSB to the multiplexer E̅ input. Draw the Z waveform.Figure 9-79 +Vcc 1
Show how a 74151 can be used to generate the logic function Z = AB + BC + AC.
Show how a 16-input multiplexer such as the 74150 is used to generate the function Z = A B CD + BCD + AB D + ABCD.
The circuit of Figure 9-80 shows how an eight-input MUX can be used to generate a four-variable logic function, even though the MUX has only three SELECT inputs. Three of the logic variables A, B,
The hardware method used in Figure 9-80 can be used to generate any four-variable logic function. For example, is implemented by following these steps:1. Set up a truth table in two halves, side by
Apply the waveforms of Figure 9-75 to the inputs of the 74ALS138 DEMUX of Figure 9-30(a) as follows:Draw the waveforms at the DEMUX outputs.Fiure 9-75Figure 9-30(a) D→ A₂ C → A₁ B→ Ao A →
For each item, indicate whether it is referring to a decoder, an encoder, a MUX, or a DEMUX.(a) Has more inputs than outputs.(b) Uses SELECT inputs.(c) Can be used in parallel-to-serial
Show how the 7442 decoder can be used as 1-to-8 demultiplexer.
Consider the system of Figure 9-31. Assume that the clock frequency is 10 pps. Describe what the monitoring panel indications will be for each of the following cases.(a) All doors closed (b) All
Draw the waveforms at transmit_data, and DEMUX outputs O0, O1, O2, and O3 in Figure 9-33 for the following register data loaded into the transmit registers in Figure 9-32: [A] = 0011, [B] = 0110, [C]
Modify the system of Figure 9-31 to handle 16 doors. Use a 74150 16-input MUX and two 74LS138 DEMUXes. How many lines are going to the remote monitoring panel?Figure 9-31 Door 0 Door 6 +5 V +5
Figure 9-81 shows an 8 × 8 graphic LCD display grid controlled by a 74HC138 configured as a decoder, and a 74HC138 configured as a demultiplexer. Draw 48 cycles of the clock and the data input
Consider the control sequencer of Figure 9-26. Describe how each of the following faults will affect the operation.(a) The I3 input of the MUX is shorted to ground.(b) The connections from sensors 3
Consider the circuit of Figure 9-24. A test of the circuit yields the results shown in Table 9-10. What are the possible causes of the malfunction?Figure 9-24Table 9-10 COUNTER SELECT TC QDQC QB
A test of the security monitoring system of Figure 9-31 produces the results recorded in Table 9-11. What are the possible faults that could cause this operation?Table 9-11Figure 9-31 Condition All
The synchronous data transmission system of Figure 9-32 and Figure 9-33 is malfunctioning. An oscilloscope is used to monitor the MUX and DEMUX outputs during the transmission cycle, with the results
A test of the security monitoring system of Figure 9-31 produces the results recorded in Table 9-12. What are the possible faults that could cause this operation? How can this be verified or
The synchronous data transmission system of Figures 9-32 and 9-33 is not working properly and the troubleshooting tree diagram of Figure 9-38 has been used to isolate the problem to the timing and
Redesign the circuit of Problem 9-16 using a 74HC85 magnitude comparator. Add a “copy overflow” feature that will activate an ALARM output if the OPERATE output fails to stop the machine when the
A technician tests the code converter of Figure 9-43 and observes the following results:What is the probable circuit fault?Figure 9-43 BCD Input 52 95 27 Binary Output 0110011 1100000 0011011
Assume a BCD input of 69 to the code converter of Figure 9-43. Determine the levels at each Σ output and at the final binary output.Figure 9-43 D₁ C₁ B₁ A₁ Do Co Bo Ao 3210 !!!! Co 74HC83 3
(a) Show how to connect 74HC85s to compare two 10-bit numbers.(b) Create a 10-bit comparator using a megafunction.
For the bus arrangement of Figure 9-47, describe the input signal requirements for simultaneously transferring the contents of register C to both of the other registers.Figure 9-47 Only one
Assume that the registers in Figure 9-47 are initially [A] = 1011, [B] = 1000, and [C] = 0111. The signals in Figure 9-83 are applied to the register inputs.(a) Determine the contents of each
True or false:(a) A device connected to a data bus should have tristate outputs.(b) Bus contention occurs when more than one device takes data from the bus.(c) Larger units of data can be transferred
Assume the same initial conditions of Problem 9-58, and sketch the signal on DB3 for the waveforms of Figure 9-83.Data from Problem 9-58Assume that the registers in Figure 9-47 are initially [A] =
Figure 9-84 shows two more devices that are to be added to the data bus of Figure 9-47. One is a set of buffered switches that can be used to enter data manually into any of the bus registers. The
Now that the circuitry of Figure 9-85 has been added to Figure 9-47, a total of five devices are connected to the data bus. The circuit in Figure 9-85(a) will now be used to generate the enable
Show how a 74HC541 (Figure 9-50) can be used in the circuit of Figure 9-84.Figure 9-84Figure 9-50 +5 V 1 ΚΩ SW3 SW2 SW1 SWO 74HC125 CLOCK- (from Figure 9-47) 1 1 Data bus from Figure 9-47 DB 3
Figure 9-86 shows the basic circuitry to interface a microprocessor (MPU) to a memory module. The memory module will contain one or more memory ICs (Chapter 12) that can either receive data from the
The keyboard entry circuit of Figure 9-16 is to be used as part of an electronic digital lock that operates as follows: when activated, an UNLOCK output goes HIGH. This HIGH is used to energize a
Write the HDL code for a hex decoder/driver for a 7-segment display. The first 10 characters should appear as shown in Figure 9-7. The last six characters should appear as shown in Figure 9-87.Figure
Write the HDL code for a BCD-to-decimal decoder (the equivalent of a 7442).
Modify the stepper design file of Figure 10-8 or 10-9 to add an enable input that puts the outputs in the Hi-Z state (tristate) when enable = 0.Figure 10-8Figure 10-9 SUBDESIGN [ig10 8. ( ) step,
Use HDL to describe a three-digit BCD code to eight-bit binary number converter. (Maximum BCD input is 255.)Figure 9-69Figure 9-70 THEODORUAWNE 7 9 10 11 SUBDESIGN fig9_69 ( a[3..0], b[3..0] agtb,
Write a low-priority ENCODER description that will always encode the lowest number if two inputs are activated simultaneously.
Rewrite the stepper driver design file of Figure 10-8 or 10-9 without using a CASE statement. Use your favorite HDL.Figure 10-8Figure 10-9 SUBDESIGN [ig10 8. ( ) step, dir m[1..0), cin 13..01 cout
The cout lines of Figure 10-1 started at 1010 and have just progressed through the following sequence: 1010, 1001, 0101, 0110.(a) How many degrees has the shaft rotated?(b) What sequence will reverse
Use HDL to describe a four-bit binary number to a two-digit BCD code converter.
Write the state table for the ring counter shown in Figure 10-11 and described in Figure 10-13.Figure 10-11Figure 10-13 CLK Hexadecimal keypad +5 V wwwww DA DO $0 $ OE PPPP R₂ R₂ P₂ C₂ C₂ $
Describe a method to test the stepper driver in:(a) Full-step mode(b) Half-step mode(c) Wave-drive mode(d) Direct-drive mode
With no keys pressed, what is the value on c[3..0]?
Assume that the ring counter is in state 0111 when someone presses the 7 key. Will the ring counter advance to the NEXT state?
Assume the 9 key is pressed and held until DAV = 1.(a) What is the value on the ring counter?(b) What is the value encoded by the row encoder?(c) What is the value encoded by the column encoder?(d)
Assume a 1-Hz clock is applied to the seconds stage of the clock in Figure 10-17. The MOD-10 units of seconds counter’s terminal count (tc) output is shown in Figure 10-51. Draw a similar diagram
In Problem 10-12, will the data be valid on the falling edge of DAV?Data from Problem 10-12Assume the 9 key is pressed and held until DAV = 1.What is the value on the ring counter?What is the value
The keypad is connected to a 74373 octal transparent latch as shown in Figure 10-50. The output is correct as long as a key is held. However, it is unable to latch data between key presses. Why will
How many cycles of the 60-Hz power line will occur in a 24-hour period? What problem do you think will result if we attempt to simulate the operation of the entire clock circuit?
Modify the hours stage of Figure 10-18 to keep military time (00–23 hours).Figure 10-18 en_hrs clock tens hrs en_hrs VCC GND 1 74160 LDN A B с D ENT ENP CLRN CLK QA QB QC QD RCO Counter Units of
Refer to Figure 10-42. Each counter block in this figure represents the lowest level of the hierarchy established for this project: a primary functional block. Its specifications are MOD 10 (or 6),
Many digital clocks are set by simply making them count faster while a push button is held down. Modify the design to add this feature.
Refer to Figure 10-43. The sub-blocks (encoder, divide-by counter, non-recycling counter, MUX) could be implemented as separate blocks in the third level of hierarchy of this project. Code can be
Refer to Figure 10-44. The block on the left is simply combinational logic that must control the S-R latch that turns on and off the magnetron tube.(a) Draw a logic diagram using only gates to
Refer to Figure 10-45. This block decodes the three BCD digits from the timer block and drives the active-LOW 7-segment LED displays. It must also accomplish leading zero blanking.(a) Use 7447
Write the HDL code for the MOD-6 control counter and control signal generator in Figure 10-49.Figure 10-49 System clock 100 kHz Decade 10 kHz Decade counter counter DIV10 DIV10 1 kHz Decade 100
Draw the hierarchy diagram for the frequency counter project.
Write the HDL code for the MUX of Figure 10-49.Figure 10-49 System clock 100 kHz Decade 10 kHz Decade counter counter DIV10 DIV10 1 kHz Decade 100
Use graphic design techniques and the BCD counter described in Figure 10-31, the MUX, and the control signal generator design to create the entire timing and control block for the frequency counter
Write the HDL code for the timing and control section of the frequency counter.
A certain DAC has the following specifications: eight-bit resolution, full scale = 2.55 V, offset ≤ 2 mV; accuracy = ±0.1% F.S. A static test on this DAC produces the results shown in Table 11-11.
Repeat Problem 11-20 using the measured data given in Table 11-12.Table 11-12Data from Problem 11-20A certain DAC has the following specifications: eight-bit resolution, full scale = 2.55 V, offset
A technician connects a counter to the DAC of Figure 11-3 to perform a staircase test using a 1-kHz clock. The result is shown in Figure 11-36. What is the probable cause of the incorrect staircase
Fill in the blanks in the following description of the ADC of Figure 11-13. Each blank may be one or more words.A START pulse is applied to _______________ the counter and to keep _______________
Connect a 2.0-V reference source to VREF/2, and repeat Problem 11-38.Data from Problem 11-38Refer to Figure 11-21. What is the approximate value of the analog input if the microcomputer’s data bus
Refer to Figure 11-21. What is the approximate value of the analog input if the microcomputer’s data bus is at 10010111 when R̅D̅ is pulsed LOW?Figure 11-21 Analog 0.5-3.5 V VREF IN
Figure 11-39 shows the waveform at VAX for a six-bit SAC with a step size of 40 mV during a complete conversion cycle. Examine this waveform and describe what is occurring at times t0 to t5. Then
Repeat Problem 11-34 for VA = 16 V.Data from Problem 11-34Draw the waveform for VAX as the SAC of Figure 11-19 converts VA = 6.7 V.Figure 11-19 To control logic From control logic COMP REGISTER R
Draw the waveform for VAX as the SAC of Figure 11-19 converts VA = 6.7 V.Figure 11-19 To control logic From control logic COMP REGISTER R Q3 G Q₂ o VA = 10.4 V MSB DAC step size =
An eight-bit digital-ramp ADC with a 40-mV resolution uses a clock frequency of 2.5 MHz and a comparator with VT = 1 mV. Determine the following values.(a) The digital output for VA = 6.000 V(b) The
Why were the digital outputs the same for parts (a) and (b) of Problem 11-24?Data from Problem 11-24An eight-bit digital-ramp ADC with a 40-mV resolution uses a clock frequency of 2.5 MHz and a
What would happen in the ADC of Problem 11-24 if an analog voltage of VA = 10.853 V were applied to the input? What waveform would appear at the D/A output? Incorporate the necessary logic in this
An ADC has the following characteristics: resolution, 12 bits; fullscale error, 0.03% F.S.; full-scale output, +5 V.(a) What is the quantization error in volts?(b) What is the total possible error in
The quantization error of an ADC such as the one in Figure 11-13 is always positive because the VAX value must exceed VA in order for the comparator output to switch states. This means that the value
For the ADC of Figure 11-37, determine the range of analog input values that will produce a digital output of 0100011100.Figure 11-37 VAY Comp Sum amp VAY = VAX +5 mV EOC VAX +5 mV D/A converter 10
Assume that the analog signal in Figure 11-38(a) is to be digitized by performing continuous A/D conversions using an eight-bit digital ramp converter whose staircase rises at the rate of 1 V every
On the sine wave of Figure 11-38(b), mark the points where samples are taken by a flash A/D converter at intervals of 75 μs (starting at the origin). Then draw the reconstructed output from the D/A
A sampled data acquisition system is being used to digitize an audio signal. Assume the sample frequency FS is 20 kHz. Determine the output frequency that will be heard for each of the following
Indicate whether each of the following statements refers to the digitalramp ADC, the successive-approximation ADC, or both.(a) Produces a staircase signal at its DAC output(b) Has a constant
A certain eight-bit successive-approximation converter has 2.55 V full scale. The conversion time for VA = 1 V is 80 μs. What will be the conversion time for VA = 1.5 V?
Discuss how a flash ADC with a conversion time of 1 μs would work for the situation of Problem 11-30.Data from Problem 11-30Assume that the analog signal in Figure 11-38(a) is to be digitized by
For each of the following statements, indicate which type of ADC— digital-ramp, SAC, or flash—is being described.(a) Fastest method of conversion(b) Needs a START pulse(c) Requires the most
For each statement, indicate what type(s) of ADC is (are) being described.(a) Uses subranging stages(b) Uses a large number of comparators(c) Uses a VCO(d) Is used in noisy industrial environments(e)
Refer to the S/H circuit of Figure 11-26. What circuit fault would result in VOUT looking exactly like VA? What fault would cause VOUT to be stuck at 0?Figure 11-26 Analog input Digital
Use the CMOS 4016 IC to implement the switching in Figure 11-27, and design the necessary control logic so that each analog input is converted to its digital equivalent in sequence. The ADC is a
Figure 11-21 shows how the ADC0804 is interfaced to a microcomputer. It shows three control signals, C̅S̅, R̅D̅, and W̅R̅, that come from the microcomputer to the ADC. These signals are used to
You have available a 10-bit SAC A/D converter (AD 573), but your system requires only eight bits of resolution and you have only eight port bits available on your microprocessor. Can you use this A/D
The data in Table 11-13 are input samples taken by an A/D converter. Notice that if the input data were plotted, it would represent a simple step function like the rising edge of a digital signal.

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