Fill in the blanks in the following description of the ADC of Figure 11-13. Each blank may be one or more words.

A START pulse is applied to _______________ the counter and to keep _______________ from passing through the AND gate into the _______________. At this point, the DAC output, V_AX, is _______________ and E̅O̅C̅ is _______________.

When START returns _______________, the AND gate is _______________, and the counter is allowed to _______________. The V_AX signal is increased one _______________ at a time until it _______________ V_A. At that point, _______________ goes LOW to _______________ further pulses from _______________. This signals the end of conversion, and the digital equivalent of V_A is present at the _______________.