Refer to Figure 10-42. Each counter block in this figure represents the lowest level of the hierarchy established for this project: a primary functional block. Its specifications are MOD 10 (or 6), BCD down counter, active-LOW synchronous load, active-LOW asynchronous clear, active-HIGH enable, positive-edge triggered, active-HIGH terminal count output (gated by enable), active-HIGH decode zero output.

(a) Create an Altera megafunction to implement this block.

(b) Write the AHDL code to implement this block.

(c) Write the VHDL code to implement this block.

Figure 10-42

Transcribed Image Text:

data[3.0] C loadn D cim clock enable INPUT Voc INPUT VOC INPUT VOC INPUT VOC D DUNPUT VOC Units of Seconds Least significant digit mod 10 data[3.0] ones(3.0] loadn cim dk Hon ins14 to zaro Tens of Seconds Middle digit mode data 3.0] tens(3.0) loadin cim cik on inst 10 zaro Minutos Most significant digit mod10 (data[3.0] ones(3.01 badn cim ck on in 5 AND3 inst3 ZO to OUTPUT HOUTPUT JOUTPUT OUTPUT sec ones3..0 sec_tan (3.0) mins(3.0) >2010