In a certain manufacturing process, a conveyor belt will shut down whenever specific conditions occur. These conditions are monitored and reflected by the states of four logic signals as follows: signal A will be HIGH whenever the conveyor belt speed is too fast; signal B will be HIGH whenever the collection bin at the end of the belt is full; signal C will be HIGH when the belt tension is too high; signal D will be HIGH when the manual override is off.

A logic circuit is needed to generate a signal x that will go HIGH whenever conditions A and B exist simultaneously or whenever conditions C and D exist simultaneously. Clearly, the logic expression for x will be x = AB + CD.

The circuit is to be implemented with a minimum number of ICs. The TTL integrated circuits shown in Figure 3-31 are available. Each IC is a quad, which means that it contains four identical gates on one chip.

Figure 3-31

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74LS32 14 13 Vcc BH! RI 3 4 5 6 GND 74LS00 74LS08 14 13 12 Vcc 3161 4 14 13 12 Vcc 5 9 5 9 6 8 GND 8 GND