Refer to Figure 7-14, where a 74HC163 has the input signals given in the timing diagram applied.

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Refer to Figure 7-14, where a 74HC163 has the input signals given in the timing diagram applied. The parallel data inputs are permanently connected as 1100. Assume the counter is initially in the 0000 state, and determine the counter output waveforms.


Figure 7-14

CLK CLR LOAD ENT ENP QD QC QB QA RCO to 1 T T I T I T 1 1 1 T 1 I T 1 I T T I I 1 T T 1 T T 1 T 1 JUL> CLK

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Digital Systems Principles And Application

ISBN: 9780134220130

12th Edition

Authors: Ronald Tocci, Neal Widmer, Gregory Moss

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