Repeat question 2 for ADD = 0, SUB = 1. Data from Question 2 Assume that [A]

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Repeat question 2 for ADD = 0, SUB = 1.


Data from Question 2

Assume that [A] = 0011 and [B] = 0010 in Figure 6-14. If ADD = 1 and SUB = 0, determine the logic levels at the OR gate outputs.


Figure 6-14

Transfer pulse BB 0 12 B3 CLK Ag { B B 6 D B register 11 B 01 CLK A A B B D 10 3 B 74LS283 A A CLK B B 2 D 1

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Digital Systems Principles And Application

ISBN: 9780134220130

12th Edition

Authors: Ronald Tocci, Neal Widmer, Gregory Moss

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