17. The protocol for a certain data bus is shown in the table below.

Draw the corresponding timing diagram. You may refer to Figure 7.11.

Time Salient Bus Signal Meaning Assert to Bus is needed for reading (not writing) Read 15 15 Assert Indicates where bytes will be written Address Assert Request Request read to address on address lines t3- Data Lines Read data (requires several cycles) t7 Assert t4 Ready Acknowledges read request, bytes placed on data lines Lower t4 Request signal no longer needed Request Lower tg Release bus Ready